/*
    General purpose registers.
*/

module gprs
(
	input	wire 	    		clk, 
	input 	wire				gpr_write_back_en,      	// Enable register write back
	input	wire	[63:0] 	    gpr_write_back_data,      	// Data for write back register
	input 	wire	[04:0] 	    gpr_write_back_id,		   	// Register to write back
	input 	wire	[04:0] 	    gpr_id1, 				    // Register number for out1
	input 	wire	[04:0] 	    gpr_id2, 				    // Register number for out2
	output	wire	[63:0] 		gpr_output1,	      		// Data out 1, available one clock after outRegId1 is set
	output 	wire	[63:0] 		gpr_output2       		    // Data out 2, available one clock after outRegId2 is set
);
	reg	[63:0]	gprs[31:0];
	
	always @(posedge clk)  begin
		if ( gpr_write_back_en && gpr_write_back_id != 5'b0 ) begin
			gprs[gpr_write_back_id] <= gpr_write_back_data;
		end
	end	

    assign gpr_output1 = ( gpr_id1 == 5'b0 ) ? 64'b0 : gprs[gpr_id1];
    assign gpr_output2 = ( gpr_id2 == 5'b0 ) ? 64'b0 : gprs[gpr_id2];
endmodule